The present invention generally relates to frequency-dividing circuits, and more particularly to a frequency-dividing circuit capable of obtaining a frequency-divided output signal, which is of a simple circuit construction comprising a relatively small number of circuit elements such as asynchronous counters and shifting circuits which can be manufactured at low cost.
Generally, in electronic instruments such as an electronic organ, the notes C, B, A.sup..music-sharp.,--, D.sup..music-sharp., D, and C.sup..music-sharp. of the musical scale, are obtained by frequency-dividing a master clock signal of 2.008448 MHz, for example, by use of a number of frequency-dividing circuits corresponding to the number of notes, where each of the frequency-dividing circuits has a frequency-dividing ratio corresponding to each note of the musical scale. These frequency-divided signals respectively having a frequency respective of each note in the musical scale, are further successively frequency-divided into one-half the original frequency at a plurality of stages. Accordingly, the signals having frequencies respectively corresponding to each note of the musical scale, that is, each key of the electronic organ, are respectively obtained from each of the one-half frequency-dividing circuits.
In the above described circuit, the frequency-dividing circuit having a frequency-dividing ratio corresponding to the E note of the musical scale, for example, is a 379-count counter which obtains a signal in which one period is an interval consisting of 379 pulses of a master clock signal. Similarly, the frequency-dividing circuit having a frequency-dividing ratio corresponding to the D.sup..music-sharp. note of the musical scale, is a 402-count counter which obtains a signal in which one period is an interval consisting of 402 pulses of the master clock signal. However, in the above example of the frequency-dividing circuit which has a frequency-dividing ratio of 1/379 (the 379-count counter), one-half the period corresponds to 189.5 pulses of the master clock signal, since the denominator of the frequency-dividing ratio when the ratio is represented in a form of unity over a number is of an odd value, namely, 379. Accordingly, in this case, it becomes necessary to detect the timing for the above interval corresponding to 0.5 pulse of the master clock signal. Therefore, in the conventional frequency-dividing circuit, the timing corresponding to the above interval of 0.5 pulse is obtained by switching the rising edge and the failing edge of the master clock signal immediately before the pulses corresponding to one-half the period are counted. However, the construction of the logic circuit which obtains the above timing to perform the switching becomes complex. Moreover, when the frequency-dividing ratio is multiplied by two together with the master clock signal, it becomes unnecessary to detect the timing for the interval corresponding to 0.5 pulse of the master clock signal, however, it becomes difficult for the operations of the circuits which comprise the frequency-dividing circuits to follow the master clock signal. Hence, in extreme cases, the operations of the circuits which comprise the above frequency-dividing circuits do not follow the master clock signal.
On the other hand, a frequency-dividing circuit has been proposed which uses a synchronized counter comprising a plurality of stages of shift registers simultaneously supplied with a master clock signal supplied through an input terminal, a decoder circuit supplied with each output of the shift registers, and a feed-back circuit having exclusive-OR logic circuits. In this proposed circuit, a reset-and-set (R-S) flip-flop circuit which is set and reset by the output of the decoder circuit into which logic data corresponding to a desired frequency-dividing ratio is pre-established, is operated, to obtain a desired frequency-divided output. However, in this circuit, the number of logic circuits used is large compared to the case where an asynchronous counter is used, since a synchronized counter is used in this case. Accordingly, the circuit construction of the above circuit becomes complex, and suffers a disadvantage in that the circuit can not be manufactured at low cost.